The design and implementation of image processing algorithms on FPGA and hardware/software co-design of space-related applications

Abstract

Software-based algorithm design is still the mainstream of preliminary development. However, how to make the algorithm perform better in practical applications has always been a research topic. The factors including overall operating speed and throughput have always been the limitations of pure software algorithms.

As the performance of hardware chips continues to improve, hardware devices such as Field-Programmable Gate Array (FPGA) can gradually perform more computational works to take on part of the tasks from the software side. Due to its specific structure and programming system, FPGA-based algorithms can be more targeted and run faster. But the register-transfer-level (RTL) design abstraction has produced a lot of difficulty in the development of complex algorithms.

This thesis presents two FPGA-based Speeded Up Robust Features (SURF) detection algorithms. One of them focuses on implementing complex applications based on floating-point arithmetic on hardware, and the other relies only on fixed-point arithmetic to seek a substantial increase in performance and efficiency while ensuring accuracy at the same time. Finally, a hardware/software (HW/SW) co-designed satellite pose estimation algorithm is proposed. The hardware side undertakes the high-efficiency algorithm based on fixed-point numbers, and the software side is responsible for the overall control and subsequent pose estimation. The core of the research lies in the overall structural design and the data transmission between modules.

Simulation, synthesis, and implementation result of all three algorithms demonstrate their functional performance and resource utilisation. It proves that the hardware-based and HW/SW co-designed image processing algorithms have obvious advantages in operational efficiency, resource utilisation and power consumption to support the use in space-related applications.