High-Speed Implementations of Spectral Correlation Analysis Techniques

Abstract

Spectral correlation density (SCD) is widely used to characterize cyclostationary signals, but its high computational requirements pose significant challenges. Although the fast Fourier transform (FFT) enables efficient methods such as the FFT accumulation method (FAM) and strip spectral correlation analyzer (SSCA), their real-time adoption remains limited. Therefore, optimizing these methods for computational efficiency is essential to balance accuracy and efficiency. This work focuses on reducing wordlength, leveraging parallel hardware architectures, and minimizing computational complexity.

This study first analyzes the relationship between wordlength and signal-to-quantization-noise ratio (SQNR) in fixed-point SCD implementation, using a canonical FAM-based estimator with both fixed- and mixed-point arithmetic. High performance is achieved on the AMD/Xilinx Zynq UltraScale+ RFSoC ZCU111 platform by exploiting spatial parallelism, pipelining, I/O optimization, and algorithmic symmetry.

Next, an SSCA implementation is proposed for large datasets on the AMD/Xilinx Versal VCK5000 platform. It utilizes parallelism across the programmable logic (PL), double data rate memory controller (DDRMC), and AI engine (AIE), and combines very-long instruction word (VLIW) and single-instruction multiple-data (SIMD) architectures. The PL handles data transfer between the DDRMC and AIE, ensuring seamless communication. This architecture maximizes hardware efficiency and throughput for large-scale processing.

Lastly, the sparse strip spectral correlation analyzer (S3CA) is introduced, employing the sparse fast Fourier transform (SFFT) to leverage the sparsity of the cyclic spectrum in practical signals. It computes a sparse, downsampled channel-data product (CDP) and applies a modified SFFT to estimate the SCD efficiently. This approach reduces computation and enhances scalability, enabling real-time spectral analysis of large datasets.