Characterisation and Modelling of Bulk CMOS Transistors over the 5 – 300 K Temperature Range

Abstract

With the increasing interest in MOSFET device operation in extremely cold environments, circuit designs for low temperature applications have attracted recent attention. Device characterisation and modelling are crucial steps in circuit designs, and an appropriate approach for transistor characterisation at cryogenic temperatures is required to provide insight into transistor behaviour, and to develop reliable models for circuit simulations over the required operating temperatures. This work presents a detailed study of bulk CMOS transistors behaviour from room temperature down to 5 K. A new approach to extract intrinsic and extrinsic parameters of bulk CMOS over a wide range of temperature is proposed. Extracted MOSFET parameters reveal changing characteristics over the examined temperatures. Transistor characteristics are modelled based on physical properties of device and empirical results. This thesis introduces an enhanced MOSFET threshold model, based on a simplified Fermi potential and a field-assisted ionisation, derived from physics and experimental data. The model predicts the threshold voltage better than the conventional model, especially at low temperatures. An adapted carrier mobility model derived from a conventional model is experimentally verified. This work also presents a Verilog-A SPICE model based on the proposed models and extraction results. The SPICE model can be incorporated into Cadence Spectre simulator for circuit simulations at low temperatures. The SPICE model can replicate the I-V characteristics of the bulk CMOS over a wide temperature range. The matching of transistors is one of the most important aspects of high performance integrated circuit design. Results from this research reveal, for the first time, the matching properties of MOSFETs and its parameters over the 5-300 K temperature range. In addition, a new formula to calculate the current matching in bulk CMOS devices based on the threshold voltage, mobility and series resistance is introduced. The proposed formula obtained better results compared to the existing formula at low temperatures. The effects of device geometries on MOSFET parameter matching and current matching are also exposed. Matching results from PMOS and NMOS devices provide a view of device parameter variations from room temperature down to 5 K.